TCP/IP Offload Engine IP Core
Overview:
Pcion’s TOE is a flexible system on a chip which supports applications demanding high network performance. The high performance small footprint SOC works at wire speeds of 1G or 10G and reduces the host CPU load by a factor of 10-100.
Pcion TCP/IP Offload Engines (TOE) are user-configurable 100% hardware accelerated cores targeting applications where the highest available network performance is desired or required. The cores are available in 1Gbps and 10Gbps versions that enable processors to perform at full wire speed (1Gbps/10Gbps) while simultaneously reducing the CPU work load by a factor of 10 – 100. This CPU workload reduction helps ensure the design engineer has the maximum number of cycles available to allocate to the primary application.
Pcion is committed to creating IP cores to the highest of industry standards. Pcion is a proud member of the UNH Interoperability Lab (IOL). The UNH-IOL is the networking industry’s premier independent proving ground for new technologies. The UNH-IOL provides rigorous one-on-one quality assurance testing as well as leading-edge facilities and support for multi-vendor group tests in nearly every facet of networking.
Find us with UNH-IOL here.
The highest possible performance is assured by Pcion’s patent-pending Rapidchek™ checksumming DMA and a proprietary optimized pipe-lined architecture that utilizes multiple concurrent processing blocks. Other important benefits of this optimized architecture are a very small logic footprint, and low power consumption.
The Pcion TOE cores enable a broad range of applications and emphasize performance, cost, scalability, feature extensibility and mission-critical reliability. Typical applications for the Pcion embedded TOEs include but are not limited to:
- Network Attached Storage (NAS) chips and systems.
- Storage Area Network (SAN) chips, boards (HBAs) and systems (RAID).
- Cloud computing and virtualization technologies.
- Medical imaging equipment.
- High bandwidth digital video (high resolution network cameras).
i-PCI IP Cores
Overview:
“I/O Anywhere™” these two words effectively summarize what i-PCI is all about. No longer is a system designer constrained by physical distance limitations as dictated by a particular I/O standard. The i-PCI protocol extends a PCIe I/O system via an IP network, an Ethernet link, or Direct Connect Ethernet physical layer link. The i-PCI protocols allows functions or adapter cards to be located geographically remote, via two implementation options, yet appear as local bus resources.
The two implementation options currently available for i-PCI are i(dc)-PCI and i(e)-PCI. Each has distinct advantages and disadvantages, depending on the applications. The i(dc)-PCI implementation is a direct physical connect approach, utilizing Ethernet Category-x (Cat-x) cables. The i(e)-PCI implementation is a LAN approach, utilizing MAC addresses and Ethernet switches.
i(dc)-PCI Implementation Option (showing three variations)
i(e)-PCI Implementation Option
An i-PCI cores solution pak is supplied as either an i(dc)-PCI or i(e)-PCI implementation and consists of the two link cores (HBA Multifunction Endpoint core, Multifunction Endpoint Function core) and two example endpoint function cores (Memory Controller, USB Controller)
HBA Multifunction Endpoint:
This core interfaces a host PCI Express bus to the network MAC. The core handles the encapsulation/de-encapsulation of the PCI Express packets within an Ethernet frame (i(e)-PCI) or within the Ethernet physical layer (i(dc)-PCI) for transport over the network.
- » For the i(dc) implementation the i(dc)-PCI HBA Multifunction Endpoint variant is specified. Two speed grades are available:
- • 1Gbps (suitable for low bandwidth demanding remote endpoint functions)
- • 10Gbps (required for high bandwidth demanding remote endpoint functions)
- » For the i(e) implementation the i(e)-PCI HBA Multifunction Endpoint variant is specified. Two speed grades are available:
- • 1Gbps (suitable for low bandwidth demanding remote endpoint functions)
- • 10Gbps (required for high bandwidth demanding remote endpoint functions)
Multifunction Endpoint Function:
This core is used at a remote location to interface between the network and an Endpoint Function. The core handles the encapsulation/de-encapsulation of the PCI Express packets within an Ethernet frame (i(e)-PCI) or within the Ethernet physical layer (i(dc)-PCI) for transport over the network.
- » For the i(dc) implementation the i(dc)-PCI Multifunction Endpoint variant is specified.
- » For the i(e) implementation the i(e)-PCI Multifunction Endpoint variant is specified.
Endpoint Function:
This core is used at a remote location to implement the desired peripheral function. Anywhere from 1 to 8 separate endpoint functions may be associated with a single HBA Multifunction Endpoint. The endpoint functions associated with a given HBA Multifunction Endpoint may all be located at a single remote location or at separate remote locations.
- » For the i(dc) implementation an i(dc)-PCI Endpoint variant is specified.
- » For the i(e) implementation an i(e)-PCI Endpoint variant is specified.
The particular Endpoint function may be selected from any of the class codes and associated subclass codes as defined the PCI Express Standard (mass storage controller, memory controller, input device, etc.). A standard endpoint PCI Express function may be readily ported to i-PCI with appropriate guidance from Pcion.
Pcion offers two basic endpoint functions: 1) Memory Controller and 2) USB Controller
- » Memory Controller Endpoint Function: This is a class code 05h, subclass 00h core which may be used for basic 32-bit I/O memory operations and interfacing to basic I/O memory.
- » USB Controller : This is a class code 0Ch, subclass 00h USB 1.1 Universal Host Controller which may be used to interface to any USB 1.1 compatible device.
i-PCI cores – the essential building blocks of an I/O Anywhere™ System.
What is i-PCI
i-PCI allows I/O resources to be
located remotely on a network yet appear to the host system and host software as native system memory